Re: [myhdl-list] Dream Mux (still a dream for now)

[Tom D. <TD...@di...>]

>     Thanks for your reply. Unfortunately, even though the above does
> convert, I think it leaves a lot to be desired because it produces
> long-winded, hard to follow Verilog code. I think it's important for the
> Verilog code to stay reaonably readable and MyHDL already does a great
> job in that respect. As far as the top-level interface, having it
> completely flat is inconvenient for me, but I can live with it for now.
> I'm going to try to find my own solution, and I'll let you know if I
> come up with anything. Yeah, Python hacking! :-)
>

Just my 2 cents worth...

I've never been concerned with what the generated Verilog code looks like. As 
a matter of fact, as long as it synthesizes (and simulates) properly, I would 
never look at it.

Tom