Re: [myhdl-list] Dream Mux (still a dream for now)

[George P. <ge...@ga...>]

> Mm. The code for 4 muxes, as can be expected.
>
> With Python 2.5, we'll be able to write mux behavior with one-liners:
>
>      z.next = b if sel else a
>
> which implies that the convertor will then simply produce 4 assign
> statements (using the Verilog one-liner counterpart).
>
>   
That sounds interesting. For synchronous logic, I'd like that to produce
one 'always' block in Verilog as opposed to N blocks.
>
> In summary, "readability" of the Verilog output is only my 3rd goal.
> The first is correctness, and the second is conversion power. As I
> try to show, the finest conversion results are sometimes obtained
> when no code is converted at all! (Because it has been taken care
> of before, by the elaboration with the Python interpreter.) And when,
> consequently, the Verilog output seems unrelated to the MyHDL input.
>
> Some of these ideas are explored on the following page:
>
>     http://myhdl.jandecaluwe.com/doku.php/cookbook:sinecomp
>
> A very good example of what I'm trying to say is here:
>
>     http://myhdl.jandecaluwe.com/doku.php/cookbook:bitonic
>
> The latter page shows that you can use structural recursion even
> when your target language or synthesis tool don't support recursion
> at all.
>
>   
Indeed! I've been having fun with that lately :-) Your cookbook examples 
are very rich with powerful and practical techniques. The more I re-read 
them the more I learn. Great job!

How difficult would it be to enhance the Verilog converter so it accepts 
dict lookups in generators?

I really want to have the ability to do this:

@always(sigs['clk'].posedge)
def Proc():
   
    sigs['dat'].next = 0

Thanks and keep up the good work,
George