Re: [myhdl-list] Dream Mux (still a dream for now)

[George P. <ge...@ga...>]

> George:
>
> Before doing anything else I would like to know whether you find the
> following solution acceptable.
>
> You could use dicts that hold signals to be muxed as follows:
>
> # begin code
> from myhdl import *
>
> def mux(z, a, b, sel):
>      @always_comb
>      def logic():
>          if sel:
>              z.next = b
>          else:
>              z.next = a
>      return logic
>
>
> def DreamMux(sigs0, sigs1, sigs_out, sel):
>
>      muxes = [mux(sigs_out[k], sigs0[k], sigs1[k], sel) for k in sigs_out]
>
>      return muxes
> # end code
>
>   
Hi Jan,

    Thanks for your reply. Unfortunately, even though the above does 
convert, I think it leaves a lot to be desired because it produces 
long-winded, hard to follow Verilog code. I think it's important for the 
Verilog code to stay reaonably readable and MyHDL already does a great 
job in that respect. As far as the top-level interface, having it 
completely flat is inconvenient for me, but I can live with it for now. 
I'm going to try to find my own solution, and I'll let you know if I 
come up with anything. Yeah, Python hacking! :-)

Thanks,
George

> Then there's the issue of the top-level interface. There you can't
> use dicts because the ports have to be mapped to Verilog primitives.
> However, this issue is different from your main concern and
> again, it's only an issue at the very top-level.
>
> As an example, this would be a top-level wrapper around the
> DreamMux design:
>
> # begin code
> # top-level with "flat" interface
> def Top(dat0, adr0, cyc0, stb0,
>          dat1, adr1, cyc1, stb1,
>          dat_out, adr_out, cyc_out, stb_out, sel):
>
>      sigs0 = dict(dat=dat0, adr=adr0, cyc=cyc0, stb=stb0)
>      sigs1 = dict(dat=dat1, adr=adr1, cyc=cyc1, stb=stb1)
>      sigs_out = dict(dat=dat_out, adr=adr_out, cyc=cyc_out, stb=stb_out)
>
>      top_inst = DreamMux(sigs0, sigs1, sigs_out, sel)
>
>      return top_inst
> # end code
>
> You can verify that it converts as follows:
>
> # begin code
> # conversion
> sel = Signal(bool(0))
> dat0, dat1, dat_out = [Signal(intbv(0)[8:]) for i in range(3)]
> adr0, adr1, adr_out = [Signal(intbv(0)[16:]) for i in range(3)]
> cyc0, cyc1, cyc_out = [Signal(bool(0)) for i in range(3)]
> stb0, stb1, stb_out = [Signal(bool(0)) for i in range(3)]
>
> toVerilog(Top,
>            dat0, adr0, cyc0, stb0,
>            dat1, adr1, cyc1, stb1,
>            dat_out, adr_out, cyc_out, stb_out, sel)
> # end code
>
> Best regards,
>
> Jan
>
>