Re: [myhdl-list] Dream Mux (still a dream for now)

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> Hi Jan,
> 
>     I've been experimenting with ways to make my Wishbone bus components 
> more robust and modular (as well as less tedious and error-prone to 
> write, theres quite a few signals). I've had a lot of success using 
> dicts to bundle signals together, but something is preventing me from 
> taking this concept all the way.
> 
> Basically, I want a 2:1 Mux that routes one of the signal bundles to its 
> output.
> 
> I pasted a "dream" Mux block at the end of my email. I want it to assign 
> every named signal in sigs_out, to its named counterpart in either sigs0 
> and sigs1, depending on the state of the select line.

> I'm curious as to why the code below doesn't work (it causes a 
> "Requirement Violation, see below), and if it can be made to work. I 
> really want this functionality.
> 
>     I think I've developed my Python chops enough to try working on your 
> MyHDL sourcecode myself, but I'm still unsure as to how it all works. I 
> just put your code through Doxygen which is going to help a lot, but 
> could you give me some hints and maybe enlighten me a little about what 
> would have to change? This has to be possible! :)

George:

Before doing anything else I would like to know whether you find the
following solution acceptable.

You could use dicts that hold signals to be muxed as follows:

# begin code
from myhdl import *

def mux(z, a, b, sel):
     @always_comb
     def logic():
         if sel:
             z.next = b
         else:
             z.next = a
     return logic


def DreamMux(sigs0, sigs1, sigs_out, sel):

     muxes = [mux(sigs_out[k], sigs0[k], sigs1[k], sel) for k in sigs_out]

     return muxes
# end code

Then there's the issue of the top-level interface. There you can't
use dicts because the ports have to be mapped to Verilog primitives.
However, this issue is different from your main concern and
again, it's only an issue at the very top-level.

As an example, this would be a top-level wrapper around the
DreamMux design:

# begin code
# top-level with "flat" interface
def Top(dat0, adr0, cyc0, stb0,
         dat1, adr1, cyc1, stb1,
         dat_out, adr_out, cyc_out, stb_out, sel):

     sigs0 = dict(dat=dat0, adr=adr0, cyc=cyc0, stb=stb0)
     sigs1 = dict(dat=dat1, adr=adr1, cyc=cyc1, stb=stb1)
     sigs_out = dict(dat=dat_out, adr=adr_out, cyc=cyc_out, stb=stb_out)

     top_inst = DreamMux(sigs0, sigs1, sigs_out, sel)

     return top_inst
# end code

You can verify that it converts as follows:

# begin code
# conversion
sel = Signal(bool(0))
dat0, dat1, dat_out = [Signal(intbv(0)[8:]) for i in range(3)]
adr0, adr1, adr_out = [Signal(intbv(0)[16:]) for i in range(3)]
cyc0, cyc1, cyc_out = [Signal(bool(0)) for i in range(3)]
stb0, stb1, stb_out = [Signal(bool(0)) for i in range(3)]

toVerilog(Top,
           dat0, adr0, cyc0, stb0,
           dat1, adr1, cyc1, stb1,
           dat_out, adr_out, cyc_out, stb_out, sel)
# end code

Best regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
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