[myhdl-list] Dream Mux (still a dream for now)

[George P. <ge...@ga...>]

Hi Jan,

    I've been experimenting with ways to make my Wishbone bus components 
more robust and modular (as well as less tedious and error-prone to 
write, theres quite a few signals). I've had a lot of success using 
dicts to bundle signals together, but something is preventing me from 
taking this concept all the way.

Basically, I want a 2:1 Mux that routes one of the signal bundles to its 
output.

I pasted a "dream" Mux block at the end of my email. I want it to assign 
every named signal in sigs_out, to its named counterpart in either sigs0 
and sigs1, depending on the state of the select line.

The signal bundles are Python dictionaries and could look something like 
this:

# -- Begin Code Paste --------------------------------------

sel = Signal(bool(0))

# Input Bundle 0
sigs0 = {}
sigs0['dat']    = Signal(intbv(0)[8:])
sigs0['adr']    = Signal(intbv(0)[16:])
sigs0['cyc']    = Signal(bool(0))
sigs0['stb']    = Signal(bool(0))

# Input Bundle 1
sigs1 = {}
sigs1['dat']    = Signal(intbv(0)[8:])
sigs1['adr']    = Signal(intbv(0)[16:])
sigs1['cyc']    = Signal(bool(0))
sigs1['stb']    = Signal(bool(0))

# Output Bundle
sigs_out = {}
sigs_out['dat'] = Signal(intbv(0)[8:])
sigs_out['adr'] = Signal(intbv(0)[16:])
sigs_out['cyc'] = Signal(bool(0))
sigs_out['cyc'] = Signal(bool(0))

MUX_INST = DreamMux(sigs0, sigs1, sigs_out, sel)

# -- End Code Paste --------------------------------------

I'm curious as to why the code below doesn't work (it causes a 
"Requirement Violation, see below), and if it can be made to work. I 
really want this functionality.

    I think I've developed my Python chops enough to try working on your 
MyHDL sourcecode myself, but I'm still unsure as to how it all works. I 
just put your code through Doxygen which is going to help a lot, but 
could you give me some hints and maybe enlighten me a little about what 
would have to change? This has to be possible! :)

Thanks,
George

# -- Begin Code Paste --------------------------------------

def DreamMux(sigs0, sigs1, sigs_out, sel):
    
    # I'd love to be able to do this,
    # but currently get errors in MyHDL:
    
    # sigs_out, sigs0, and sigs1 are dicts
    
    def Muxer():
        
        while True:
            
            yield sel
        
            if sel:
                                
                # For all signals in sigs_out
                # connect them to their counterparts in sigs1
                for k in sigs_out.keys():
                    sigs_out[k].next = sigs1[k]
            
            else:

                # For all signals in sigs_out
                # connect them to their counterparts in 
sigs0                
                for k in sigs_out.keys():
                    sigs_out[k].next = sigs0[k]
                    
    MUXER = Muxer()
    
    return instances()

# -- End Code Paste --------------------------------------

Traceback (most recent call last):
  File "myhdl_class_wbc_Master_Slave.py", line 282, in ?
    toVerilog(top, clk_i)
  File "/usr/lib/python2.4/site-packages/myhdl/_toVerilog/_convert.py", 
line 118
, in __call__
    _convertGens(genlist, vfile)
  File "/usr/lib/python2.4/site-packages/myhdl/_toVerilog/_convert.py", 
line 271
, in _convertGens
    compiler.walk(ast, v)
  File "/tmp/python.340/usr/lib/python2.4/compiler/visitor.py", line 
106, in wal
k
  File "/tmp/python.340/usr/lib/python2.4/compiler/visitor.py", line 63, 
in preo
rder
  File "/tmp/python.340/usr/lib/python2.4/compiler/visitor.py", line 57, 
in disp
atch
  File "/usr/lib/python2.4/site-packages/myhdl/_toVerilog/_convert.py", 
line 712
, in visitModule
    self.visit(stmt)
  File "/tmp/python.340/usr/lib/python2.4/compiler/visitor.py", line 57, 
in disp
atch
  File "/usr/lib/python2.4/site-packages/myhdl/_toVerilog/_convert.py", 
line 892
, in visitFunction
    self.visit(stmt)
  File "/tmp/python.340/usr/lib/python2.4/compiler/visitor.py", line 57, 
in disp
atch
  File "/usr/lib/python2.4/site-packages/myhdl/_toVerilog/_convert.py", 
line 647
, in visitIf
    self.mapToIf(node, *args)
  File "/usr/lib/python2.4/site-packages/myhdl/_toVerilog/_convert.py", 
line 694
, in mapToIf
    self.visit(suite)
  File "/tmp/python.340/usr/lib/python2.4/compiler/visitor.py", line 57, 
in disp
atch
  File "/usr/lib/python2.4/site-packages/myhdl/_toVerilog/_convert.py", 
line 817
, in visitStmt
    self.visit(stmt)
  File "/tmp/python.340/usr/lib/python2.4/compiler/visitor.py", line 57, 
in disp
atch
  File "/usr/lib/python2.4/site-packages/myhdl/_toVerilog/_convert.py", 
line 567
, in visitFor
    self.require(node, f in (range, downrange), "Expected (down)range call")
  File "/usr/lib/python2.4/site-packages/myhdl/_toVerilog/__init__.py", 
line 113
, in require
    self.raiseError(node, _error.Requirement, msg)
  File "/usr/lib/python2.4/site-packages/myhdl/_toVerilog/__init__.py", 
line 108
, in raiseError
    raise ToVerilogError(kind, msg, info)
myhdl.ToVerilogError: in file myhdl_class_wbc_Master_Slave.py, line 90:
    Requirement violation: Expected (down)range call