Re: [myhdl-list] PhoenixSID 65X81 News page updated

[Jan D. <ja...@ja...>]

Tom Dillon wrote:
> On Tuesday 26 September 2006 18:09, George Pantazopoulos wrote:
> 
>>>>Also, the User-defined Verilog feature won't work because it would
>>>>create
>>>>nested modules that I confirmed do NOT work in Xilinx ISE.
>>>
>>>I don't understand what you are saying won't work in ISE. Could you
>>>provide an
>>>example?
>>
>>The User-defined Verilog works great and just as advertised for inserting
>>module instantiations into the MyHDL-generated Verilog code. I didn't mean
>>to imply it was broken in some way.
>>
>>What I mean is that I can't use that feature to declare additional, needed
>>modules because it is only capable of inserting stuff *inside* existing
>>modules.
> 
> 
> I see what you are saying. I would still let ISE compile the files separately. 
> That is the normal way of doing it and really doesn't cause any trouble.

I agree with that. This thread is really about Verilog project
management and I don't think MyHDL should play a role in that.

Because of the way it works (elaborating and flattening hierarchy),
the convertor generates one single Verilog output file. This makes it
easy to set up simple projects. But that doesn't mean that having
everything in one big file is the proper way to do project management
in larger projects.

As a last resort, you always have the choice of writing your own
convenience function that concatenates files and call it right
after the conversion in your Python file. But personally I would
set up the project properly, tracking dependencies with make or
in whatever way a project environment like ISE does it.

Jan

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