Re: [myhdl-list] Beginners question

[Jan D. <ja...@ja...>]

Thomas Heller wrote:
> Jan Decaluwe schrieb:
> 
>>Thomas Heller wrote:
>>
>>>If I have two or more events in an always decorator:
>>>
>>>@always(a.negedge, b.negedge, delay(10))
>>>def func():
>>>    ...
>>>
>>>how can I determine inside func which event is currently handled?
>>
>>Currently there is no direct way. For edges and signals, it may
>>be possible to support this by making sure that certain
>>attributes (e.g. 'negedge') can be checked in code. But that
>>is not possible currently (that is, it won't work as expected).
>>For other things, such as delays, it's not clear how to do it.
>>
>>However, do we actually need this?
>>For synthesizable code, the classic synthesis templates are such
>>that the relevant checks are done implicitly by the
>>top-level if-then-else structure.
>>
>>For non-synthesizable code, you have the option of using
>>separate always blocks, each triggered by the relevant condition.
>>

> 
> Well, I guess the answer is "don't do this" anyway.

I'm open to being convinced if I understand the application.
If we look at VHDL versus Verilog: VHDL has such attributes,
Verilog doesn't. But on the other hand, you can't specify
"edges" in VHDL sensitivity lists, while you can in Verilog.
In this regard, MyHDL follows the Verilog scheme, which
suggests that we don't need the attributes either.

 > It seems
> I have still to switch from the more software oriented mental model back
> to hardware oriented.

Perhaps we can help (and also understand the original question better)
if you tell us more about your application. E.g. for the coding style
it makes a big difference whether you want to write synthesizable code
or high-level models.

Jan

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