Re: [myhdl-list] PhoenixSID 65X81 News page updated

[Tom D. <TD...@di...>]

On Tuesday 26 September 2006 18:09, George Pantazopoulos wrote:
> >> Also, the User-defined Verilog feature won't work because it would
> >> create
> >> nested modules that I confirmed do NOT work in Xilinx ISE.
> >
> > I don't understand what you are saying won't work in ISE. Could you
> > provide an
> > example?
>
> The User-defined Verilog works great and just as advertised for inserting
> module instantiations into the MyHDL-generated Verilog code. I didn't mean
> to imply it was broken in some way.
>
> What I mean is that I can't use that feature to declare additional, needed
> modules because it is only capable of inserting stuff *inside* existing
> modules.

I see what you are saying. I would still let ISE compile the files separately. 
That is the normal way of doing it and really doesn't cause any trouble.

Tom