[myhdl-list] Signal bundling experiment using dicts

[George P. <ge...@ga...>]

I did an experiment using dictionaries to bundle certain defined groups
of signals. I had some success with internal modules, but I wasn't able
to bundle the signals for the top module and get correct Verilog output.
(see below).

I also couldn't use the dict directly inside modules, (see wbcMaster)
which is also desirable in certain cases (sometimes it makes things
too cluttered, though)

Even with that limitation, bundling the signals using dicts
seems very attractive.

Of course, it would be even better to be able to do this with
the top module.

Feedback would be appreciated.

Thanks,
George

--- Begin code paste ---------

# myhdl_signal_bundling_experiment.py
# George Pantazopoulos
# MyHDL 0.5.1 signal bundling experiment using Python dicts
# 26 Sep 2006

from myhdl import *

#--------------------------------------------------------
# Signal bundling switch. Change and rerun this script
#
# Set to True to try bundling the top-level signals
# Set to False to use the default seperate signals
# -------------------------------------------------------
bundle_top_sigs = False

# 
----------------------------------------------------------------------------

# Toy Wishbone Master
def wbcMaster(master_sigs):

    # Unbundle the MASTER signals
    clk_i = master_sigs['clk_i']
    rst_i = master_sigs['rst_i']
    adr_o = master_sigs['adr_o']

    count = Signal(intbv(0)[8:])

    @always(clk_i.posedge)
    def Foo():

        if rst_i:
            count.next = 0
        else:
            count.next = (count + 1)
            adr_o.next = count

            # Note, we currently can't do this in MyHDL:
            # Though, it would be nice :)
            #master_sigs['adr_o'].next = count

    return instances()

# 
----------------------------------------------------------------------------

# External system controller connections.
# They are meant to link up with the top module's inputs
clk = Signal(bool(0))
rst = Signal(bool(0))

# SYSCON signal bundle
syscon_sigs = {}
syscon_sigs['clk_o'] = Signal(bool(0))
syscon_sigs['rst_o'] = Signal(bool(0))


# Top level module instantiation.


# Being able to bundle the signals for the top level module
# is desirable, but as of MyHDL 0.5.1 this does not seem to
# be supported
if bundle_top_sigs:

    print "--------------------------------"
    print " Using Bundled top-level signals"
    print "--------------------------------"
    print ""

    def top(syscon_sigs):

        master_sigs = {}

        master_sigs['clk_i'] = syscon_sigs['clk_o']
        master_sigs['rst_i'] = syscon_sigs['rst_o']
      
        master_sigs['adr_o'] = Signal(intbv(0)[16:])

        WBCM = wbcMaster(master_sigs)

        return instances()

    toVerilog.name = "myhdl_signal_packing_top_sigs_bundled"
    toVerilog(top, syscon_sigs)

    print "Created " + toVerilog.name + ".v"

# 
----------------------------------------------------------------------------

# Top signals seperate (the usual style)
else:


    print "---------------------------------"
    print " Using seperate top-level signals"
    print "---------------------------------"
    print ""
  
    def top(clk_i, rst_i):

        master_sigs = {}
        master_sigs['clk_i'] = clk_i
        master_sigs['rst_i'] = rst_i
      
        master_sigs['adr_o'] = Signal(intbv(0)[16:])

        WBCM = wbcMaster(master_sigs)

        return instances()
  
    toVerilog.name = "myhdl_signal_packing_top_sigs_separate"
    toVerilog(top, clk, rst)

    print "Created " + toVerilog.name + ".v"
   

# 
----------------------------------------------------------------------------

--------------------------------------------
Verilog code for Bundled top module signals:
--------------------------------------------

module myhdl_signal_packing_top_sigs_bundled (

);


reg [7:0] _WBCM_count;
wire _WBCM_rst_i;
reg [15:0] _WBCM_adr_o;


assign _WBCM_rst_i = 0;
always @(posedge _WBCM_clk_i) begin: 
_myhdl_signal_packing_top_sigs_bundled_WBCM_Foo
    if (_WBCM_rst_i) begin
        _WBCM_count <= 0;
    end
    else begin
        _WBCM_count <= (_WBCM_count + 1);
        _WBCM_adr_o <= _WBCM_count;
    end
end

endmodule



---------------------------------------------
Verilog code for separate top module signals:
---------------------------------------------

module myhdl_signal_packing_top_sigs_separate (
    clk_i,
    rst_i
);

input clk_i;
input rst_i;

reg [7:0] _WBCM_count;
reg [15:0] _WBCM_adr_o;


always @(posedge clk_i) begin: 
_myhdl_signal_packing_top_sigs_separate_WBCM_Foo
    if (rst_i) begin
        _WBCM_count <= 0;
    end
    else begin
        _WBCM_count <= (_WBCM_count + 1);
        _WBCM_adr_o <= _WBCM_count;
    end
end

endmodule