Re: [myhdl-list] PhoenixSID 65X81 News page updated

[George P. <ge...@ga...>]

>> Also, the User-defined Verilog feature won't work because it would
>> create
>> nested modules that I confirmed do NOT work in Xilinx ISE.
>>
>
> I don't understand what you are saying won't work in ISE. Could you
> provide an
> example?
>

The User-defined Verilog works great and just as advertised for inserting
module instantiations into the MyHDL-generated Verilog code. I didn't mea=
n
to imply it was broken in some way.

What I mean is that I can't use that feature to declare additional, neede=
d
modules because it is only capable of inserting stuff *inside* existing
modules.

Something like this is not legal Verilog:

-- Begin example ----------------------------

// MyHDL-generated module
module top(...);

 // Verilog component from open-source library.
 module core(...);
   ... stuff ...
 endmodule

 core CORE_INST(...);

endmodule
-- End example -----------------------------

What I need is something like this:

-- Begin example ----------------------------


// contents of core.v pasted in by MyHDL
module core(...);

endmodule


// MyHDL-generated top module
module top(...);

  cor CORE_INST(...);

endmodule

-- End example -----------------------------

The above might be better done with an `include "core.v" or maybe an
`include "myhdl_verilog_deps.v" or something to that effect. I'm not sure
right now, and my Verilog skills could still use some sharpening.

George

--=20
George Pantazopoulos
http://www.gammaburst.net