Re: [myhdl-list] PhoenixSID 65X81 News page updated
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From: Tom D. <TD...@di...> - 2006-09-26 21:04:03
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> Also, the User-defined Verilog feature won't work because it would create > nested modules that I confirmed do NOT work in Xilinx ISE. > I don't understand what you are saying won't work in ISE. Could you provide an example? |