Re: [myhdl-list] PhoenixSID 65X81 News page updated

[George P. <ge...@ga...>]

>> For my Verilog wrapping to be fully useful, I need MyHDL to do somethi=
ng
>> new.
>>
>> The problem right now is that I need to manually add any external
>> Verilog
>> files to Xilinx ISE's project manager or else the MyHDL output won't
>> synthesize due to missing modules.
>>
>> I'd love for MyHDL to automate this by slurping up any Verilog
>> dependencies specified in the MyHDL code and including them with its o=
wn
>> Verilog output.
>>
>
> I would recommend a makefile or a python script to automate this proces=
s
> for
> you.
>

I think your idea is reasonable, but having MyHDL handle it would be much
more powerful. It would allow MyHDL-wrapped Verilog modules to be treated
just like any other MyHDL module (from a synthesis standpoint anyway).

Also, the User-defined Verilog feature won't work because it would create
nested modules that I confirmed do NOT work in Xilinx ISE.

I believe it wouldn't be too hard to integrate this feature. It mainly
involves file reads and writes. No interpretation necessary.

I don't expect pure MyHDL simulation would be possible though, but
cosimulating with the user-included Verilog files should just work, right
Jan?

George

--=20
George Pantazopoulos
http://www.gammaburst.net