Re: [myhdl-list] PhoenixSID 65X81 News page updated

[Tom D. <TD...@di...>]

> For my Verilog wrapping to be fully useful, I need MyHDL to do something
> new.
>
> The problem right now is that I need to manually add any external Verilog
> files to Xilinx ISE's project manager or else the MyHDL output won't
> synthesize due to missing modules.
>
> I'd love for MyHDL to automate this by slurping up any Verilog
> dependencies specified in the MyHDL code and including them with its own
> Verilog output.
>

I would recommend a makefile or a python script to automate this process for 
you.