Re: [myhdl-list] PhoenixSID 65X81 News page updated

[George P. <ge...@ga...>]

> George Pantazopoulos wrote:
>> This may be of interest. My verilog-wrapping and WISHBONE modules are
>> still experimental, but at some point I'd like to share them:
>>
>> http://myhdl.jandecaluwe.com/doku.php/projects:phoenixsid_65x81
>
> George:
>
> It's about time to announce all your achievements and the project page
> in comp.arch.fpga. I would think there is a large interested
> public over there (including FPGA vendors watching carefully.)
>
> Or do you prefer me to do it :-) ?
>

I'll take that as a complement, thanks! :-) Sounds like you have more
"street cred" in comp.arch.fpga right now, so I think you'd be a better
choice. I don't think I'm ready just yet, but feel free to ask again :-)

For my Verilog wrapping to be fully useful, I need MyHDL to do something =
new.

The problem right now is that I need to manually add any external Verilog
files to Xilinx ISE's project manager or else the MyHDL output won't
synthesize due to missing modules.

I'd love for MyHDL to automate this by slurping up any Verilog
dependencies specified in the MyHDL code and including them with its own
Verilog output.

For example, I could give the toVerilog convertor a set of (verilog)
filenames, or even a directory name. It then reads in all those files and
combines them with the Verilog output. The "combining" is simply pasting
the  text in somehow with the MyHDL-generated Verilog; no interpretation
necessary.

This could be as simple as appending them all to the MyHDL Verilog output
file. Alternatively, it could create a seperate verilog output file or
files containing all the "dependencies". That way, the MyHDL output would
be completely ready to use, without the user needing external knowledge
about which Verilog files to include into their synthesis tool's project.

It sounds pretty simple. What do you think?

George



> Jan
>
> --
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>
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--=20
George Pantazopoulos
http://www.gammaburst.net