Re: [myhdl-list] Can classes be used to synthesize hardware?

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
>>> Can classes be used to create synthesizable Verilog? I've tried but was
>>>unsuccessful (mostly getting cryptic "AssertionError" exceptions). I'm
>>>really confused as to how this is supposed to work.
>>
>>I don't know. I haven't even started to think about if and how
>>classes could be useful for "implementation-oriented" modeling.
>>Definitely the convertor now implicitly assumes that one is using
>>generator functions, not methods. Methods would require handling
>>the "self" reference and its attributes and mapping them to Verilog
>>somehow - a completely different mechanism than what the convertor
>>can do today.
> 
> 
> Ahh, no problem. It was just one of crazy experiments. I'm much more
> comfortable  using generators right now,

Upon rereading I'd like to stress to all readers that the restrictions
mentioned are *only* related to code that is intended for conversion.
Of course, that is an important and crucial application, but not the
only one. One should appreciate the difficulties related to converting
an extremely dynamic "scripting" language to HDLs such as Verilog
and VHDL. This leads to very important restrictions. But these should
not get in the way for high-level modeling.

For modeling, MyHDL intends (and succeeds I believe) to be extremely
general. There is e.g. no problem using classes and generator
methods, and they can be very useful for high-level modeling.
As a result and because of the power of Python, you can do things
that you couldn't dream of in classical HDLs.

Just one example: a dynamic sensitivity list (that is, the list of
things that a generator waits on is created dynamically, at run time.)
I had once an example where that was natural and useful, but it's an
unknown concept in classical HDLs (I hereby claim the invention :-)).

> except for cases where there are
> many signals which can cause long, cumbersome argument lists at times. I'm
> curious if there any "tricks" to manage that complexity

There may be several possibilities. Perhaps best to discuss
on a relevant example.

> In any case, I'd much rather have native bidirectional/tristate support :-)

I'm working on it :-)

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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