Re: [myhdl-list] Can classes be used to synthesize hardware?

[George P. <ge...@ga...>]

>>  Can classes be used to create synthesizable Verilog? I've tried but w=
as
>> unsuccessful (mostly getting cryptic "AssertionError" exceptions). I'm
>> really confused as to how this is supposed to work.
>
> I don't know. I haven't even started to think about if and how
> classes could be useful for "implementation-oriented" modeling.
> Definitely the convertor now implicitly assumes that one is using
> generator functions, not methods. Methods would require handling
> the "self" reference and its attributes and mapping them to Verilog
> somehow - a completely different mechanism than what the convertor
> can do today.

Ahh, no problem. It was just one of crazy experiments. I'm much more
comfortable  using generators right now, except for cases where there are
many signals which can cause long, cumbersome argument lists at times. I'=
m
curious if there any "tricks" to manage that complexity.

In any case, I'd much rather have native bidirectional/tristate support :=
-)

Regards,
--=20
George Pantazopoulos
http://www.gammaburst.net