Re: [myhdl-list] Can classes be used to synthesize hardware?

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> Hey all,
>  Can classes be used to create synthesizable Verilog? I've tried but was
> unsuccessful (mostly getting cryptic "AssertionError" exceptions). I'm
> really confused as to how this is supposed to work.

I don't know. I haven't even started to think about if and how
classes could be useful for "implementation-oriented" modeling.
Definitely the convertor now implicitly assumes that one is using
generator functions, not methods. Methods would require handling
the "self" reference and its attributes and mapping them to Verilog
somehow - a completely different mechanism than what the convertor
can do today.

Jan

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