[myhdl-list] Can classes be used to synthesize hardware?

[George P. <ge...@ga...>]

Hey all,
 Can classes be used to create synthesizable Verilog? I've tried but was
unsuccessful (mostly getting cryptic "AssertionError" exceptions). I'm
really confused as to how this is supposed to work.

 If this is possible, could I see a tiny example?

Thanks,

--=20
George Pantazopoulos
http://www.gammaburst.net