[myhdl-list] Verilog Bidirectional tristateable bus example

[George P. <ge...@ga...>]

Hi all,
    I managed to create a dual-unidirectional to bidirectional bus adapter
in Verilog and boil it down to a simple example (see below).

    This actually worked on my Digilent Spartan3 board! (tested using
switches and buttons).

    Jan, how could we get MyHDL to output Verilog code like this? What 
would
the MyHDL input have to look like?

What modifications are necessary to MyHDL 0.5.1? If we could do this,
then I believe that would enough to allow me to access an external SRAM 
chip
and do it all from within MyHDL!

Thanks,
George
   

// George Pantazopoulos
// Bidirectional tristateable bus example
// http://www.gammaburst.net

/////////////////////////////////////////////////////////////////////////////
//
//      --------------------------
// --/->| din         "Module Z" |
//      |                        |
// --->o| /OE                    |
//      |                        |
//      |                bi_data |<--/--->
//      |                        |
//      |                        |
// <-/--| dout                   |
//      --------------------------
//
//
// - If /OE is low, then:
//          bi_data is driven with din.
//          dout is driven with 0xA.
//
// - Otherwise,
//          bi_data's output drivers are tristated.
//          dout follows bi_data (external device must drive bi_data).
//
module top(bi_data, dout, din, nOE);

parameter DATA_BITS = 4;

// Note: inout
inout  [DATA_BITS-1:0] bi_data;
wire   [DATA_BITS-1:0] bi_data;

input  [DATA_BITS-1:0] din;
wire   [DATA_BITS-1:0] din;

output [DATA_BITS-1:0] dout;
wire   [DATA_BITS-1:0] dout;

input nOE;
wire  nOE;

assign bi_data = !nOE ? din : { DATA_BITS {1'bz} };

assign dout    = !nOE ? 4'hA : bi_data;

endmodule