Re: [myhdl-list] Tristate bus to external SRAM
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From: Jan D. <ja...@ja...> - 2006-09-18 18:46:47
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George Pantazopoulos wrote: > > Wow, so toVHDL is alive. I thought we didn't need it :) Me too. But that was 2 years ago :-) I have changed my mind because of the following reasons. First, from the feedback I got it is clear that VHDL is more popular than I anticipated, especially in the FPGA world. Naturally, a tool has more chance of adoption if it plays well with existing design flows. A related second reason is that having both Verilog and VHDL output from a single source creates a capability that is afaik unique: designing IP blocks once and creating equivalent RTL-level Verilog and VHDL automatically. That must be an attractive proposition to IP developers. Third, I found a way to solve the issue of how to verify the VHDL output without need for co-simulation. I'm using a prototype of this currently - works great. And fourth, it was time for a new intellecual challenge :-) Regards, Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Losbergenlaan 16, B-3010 Leuven, Belgium From Python to silicon: http://myhdl.jandecaluwe.com |