Re: [myhdl-list] Tristate bus to external SRAM

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:

> Great to hear from you again Jan!

As from you. I notice that many people find their way to the MyHDL
pages from your fpga synth project (although not many seem to
follow your path and go for it themselves :-). What are you
doing with this project - do you share it with other enthousiast?
Plans to open source it? or commercial plans?

> I will try out your and Gunter's suggestions. What I'd like is an
> automatic way to combine the myhdl code with a user-supplied top-level
> Verilog wrapper.
> 
> This might be doable with shell scripting and/or make, but being able to
> specify the wrapper filename inside the myHDL code sounds like a better
> way right now. MyHDL could automatically incorporate the wrapper into its
> Verilog output. I'll have to experiment a bit to be sure, but what do you
> think?

At some point I would like to take some time to think thorougly
about tristates and inouts and come up with a satisfactory
solution, hopefully based on user inputs and feedback.
Currently, I'm focussed on getting toVHDL on track
and right - which offers more than enough brain teasers :-)

Jan

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Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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