Re: [myhdl-list] Tristate bus to external SRAM

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
>>Hi all,
>>
>>   I'm gettin' hungry to do some more FPGA stuff again. Could anyone give
>>me some pointers on how a tristate data bus could be implemented in
>>myHDL?
>>
> 
> 
>      Maybe I should be more clear. I'm looking to create a *bidirectional*
> bus to an external SRAM chip. I suppose somehow the output driver
> needs to get tristated when the the bus is in input mode. I'm not
> sure how to bring this about, or if the fpga software tool will infer
> this for me, etc.
> 
> Any advice would be great!

I've deliberately neglected the issue because I believe there's
hardly a good reason to use tristates *on-chip*.

But you are talking about off-chip of course. Let's separate
the issues:

Modeling
--------

In 0.5 it is possible to use None as a value for an intbv:

http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5#backwards_incompatible_changes

The idea is to use None to represent a tristate value. I believe this
is quite appropriate.

When you use a None value in an expression, you will easily get
tracebacks. Also this I think is appropriate. In other words,
I don't plan to extend operator support for intbv's to do something
"meaningful" with None values. The designer should surround such
expressions with tests for appropriate usage. (E.g. note that
any value is larger than None in Python.)

Verilog conversion support
--------------------------

Nothing has been done. At least 2 things would be needed:
1) convert a None constant value to 'Z'
2) infer inout ports at the top-level interface when
an interface signal is used as such.

In addition, it would be nice to know what templates are
exactly supported by the mainstream fgpa synthesis tools
to infer tristates, tristate ports, and bidirectional ports.
This may influence Verilog conversion choices.

Because of 2), you cannot simply use the user-defined verilog
feature to specify the verilog code you want yourself.
I fear the workaround at this point is a manually written
top-level Verilog wrapper, as suggested elsewhere.

For a possible implementation of the features discussed
above, I need feedback from users to find out and specify
exactly what needs to be done, and how urgent it is.

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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