[myhdl-list] Bitonic sort circuit

[Jan D. <ja...@ja...>]

Hi:

Recently there has been a discussion on comp.lang.verilog
about recursive structures and their synthesizability.
The bitonic sort algorithm served as an example.

I have coded a bitonic sorter circuit in MyHDL and set up
a cookbook page about it. Basically, the page describes how
to code recursive structures in MyHDL. It also illustrates
that Verilog code generation occurs after elaboration.
Consequently, the generated Verilog code is no longer
recursive. Therefore, it doesn't matter whether the back-end
language or tools support recursion or not. See:

     http://myhdl.jandecaluwe.com/doku.php/cookbook:bitonic

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com