Re: [myhdl-list] Tristate bus to external SRAM

[George P. <ge...@ga...>]

>>
>>      Maybe I should be more clear. I'm looking to create a
>> *bidirectional*
>> bus to an external SRAM chip. I suppose somehow the output driver
>> needs to get tristated when the the bus is in input mode. I'm not
>> sure how to bring this about, or if the fpga software tool will infer
>> this for me, etc.
>>
>
> You could try doing a multiplexer in Verilog and interface that to your
> Python code. Something like this:
>
>       MyHDL       |       Verilog
>                   |
>                        +\
>       Write data ----->+ \
>                        |  +<----->
>       Read data  <-----+ /
>                        +/
>                   |

I'll check that out, thanks. I also came across a verilog tutorial for
bidirectional/tristate here:
http://www.quicklogic.com/images/quicknote36.pdf#search=3D%22verilog%20tr=
istate%22

module example (OE, in1, in2, bi_ext, tri_ext);
input OE, in1, in2;
inout bi_ext;
output tri_ext;
wire bi_ext =3D OE ? (in1 & in2) : 1=92bz;
wire tri_ext =3D OE ? (bi_ext | in2) : 1=92bz;
endmodule

So between those two I think I can get something to work. Any tips on how
to smoothly integrate this with myHDL?

Thanks,

--=20
George Pantazopoulos
http://www.gammaburst.net