Re: [myhdl-list] Tristate bus to external SRAM

[Guenter D. <dan...@we...>]

George Pantazopoulos wrote:
>> Hi all,
>>
>>    I'm gettin' hungry to do some more FPGA stuff again. Could anyone give
>> me some pointers on how a tristate data bus could be implemented in
>> myHDL?
>>
> 
>      Maybe I should be more clear. I'm looking to create a *bidirectional*
> bus to an external SRAM chip. I suppose somehow the output driver
> needs to get tristated when the the bus is in input mode. I'm not
> sure how to bring this about, or if the fpga software tool will infer
> this for me, etc.
> 

You could try doing a multiplexer in Verilog and interface that to your
Python code. Something like this:

      MyHDL       |       Verilog
                  |
                       +\
      Write data ----->+ \
                       |  +<----->
      Read data  <-----+ /
                       +/
                  |


You would also need a control signal to specify the direction.

Maybe that works?

Cheers,

Guenter