[myhdl-list] Re: List of Signals as input/output in a toVerilog()

[Jan D. <ja...@ja...>]

Guenter Dannoritzer wrote:

> There is a restriction to what type of signals can be converted with
> toVerilog:
> 
> http://www.jandecaluwe.com/Tools/MyHDL/manual/conv-subset-types.html

This describes the restriction for code inside generator functions.
I guess I'll have to add a specific section about the (more severe)
restrictions for the top-level interface of a module. In fact,
only Signals with intbv, bool or enum base types can be
converted.

Regards,

Jan

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