[myhdl-list] Re: List of Signals as input/output in a toVerilog()

[Jan D. <ja...@ja...>]

Jens Petter Abrahamsen wrote:
> Hi.
> 
> I've been experimenting much with MyHDL, I like it, and I'd like to 
> make  some synthesizeable code real soon. I don't have any Verilog/VHDL  
> experience, maybe my questions are very basic.
> 
> All the examples I've seen of MyHDL->Verilog has a set number of  
> input/output signals. I'd like to create a program which has all the  
> signals inside a list (to be more flexible).
> 
> Consider the following example:
> 
> def make_many_sregs(clk,din,WIDTH,out,reset,enable,NR_REGS):
>     inst = [shiftreg(clk,din[i],WIDTH,out[i],reset,enable) for i in  
> range(NR_REGS)]
>     return inst
> 
> def convert_shiftregister_to_verilog():
>     clk,reset,enable = [Signal(bool(0)) for i in range(3)]
>     WIDTH=8
>     NR_REGS=2
>     out = [Signal(intbv(0)[WIDTH:]) for i in range(NR_REGS)]
>     din = [Signal(bool(0)) for i in range(NR_REGS)]
> 
>     toVerilog.name="shiftregister"
>     toVerilog(make_many_sregs,clk,din,WIDTH,out,reset,enable,NR_REGS)
> 
> The intention is that NR_REGS gives how many shift-registers I'd like. 
> I  make the same number of data in and parallel out Signals as  
> shift-registers.
> This is the generated Verilog code. Where are din/out signals?

They are not there, basically because there is no straightforward way
to map list of signals in an interface to a Verilog object. Verilog
memories cannot be used in an interface. (I'm not considering
SystemVerilog for the time being.)

> I also get complaints that Signals are either not driven or used when  
> keeping signals in a list.

That is a symptom of the above. The signal drivers are not "found"
because lists in interfaces are not considered. Not that this
only affects the top-level interface, because the other ones
are flattened out by the convertor.

This case violates the idea that if toVerilog() succeeds without errors,
then a MyHDL simulation and the converted Verilog simulation should
do the same. So there should be errors and no output instead of
warnings.

However, I cannot just turn the warnings into errors - in other
case people want this behavior (and the simulations will match).
Also, I don't want to do strict typechecking on the MyHDL interface,
in order to allow powerful parametrization. (toVerilog() works on
a particular instance and doesn't need the parameters.) So I'll
have to think about this further.

So, at the top-level you'll have to use individual signals at
this moment. However, once you have done that you can still
proceed with lists as follows:

def top(din1, din2, ..., dinn, dout1, dout2, ...doutn, ...):
    din = [din1, din2, ..., dinn] # cut and paste from interface
    dout = [dout1, dout2, ..., doutn]

    # now use list syntax here
    ...

Regards,

Jan

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