[myhdl-list] Re: List of Signals as input/output in a toVerilog()

[Guenter D. <dan...@we...>]

Jens Petter Abrahamsen wrote:
> Hi.
> 
> I've been experimenting much with MyHDL, I like it, and I'd like to make
> some synthesizeable code real soon. I don't have any Verilog/VHDL
> experience, maybe my questions are very basic.
> 
> All the examples I've seen of MyHDL->Verilog has a set number of
> input/output signals. I'd like to create a program which has all the
> signals inside a list (to be more flexible).
> 
> Consider the following example:
> 
> def make_many_sregs(clk,din,WIDTH,out,reset,enable,NR_REGS):
>     inst = [shiftreg(clk,din[i],WIDTH,out[i],reset,enable) for i in
> range(NR_REGS)]
>     return inst
> 
> def convert_shiftregister_to_verilog():
>     clk,reset,enable = [Signal(bool(0)) for i in range(3)]
>     WIDTH=8
>     NR_REGS=2
>     out = [Signal(intbv(0)[WIDTH:]) for i in range(NR_REGS)]
>     din = [Signal(bool(0)) for i in range(NR_REGS)]
> 
As an example din is:

din = [Signal(False), Signal(False), Signal(False), Signal(False)]

... a list of signals.

There is a restriction to what type of signals can be converted with
toVerilog:

http://www.jandecaluwe.com/Tools/MyHDL/manual/conv-subset-types.html


Cheers,

Guenter