[myhdl-list] List of Signals as input/output in a toVerilog()

[Jens P. A. <je...@if...>]

Hi.

I've been experimenting much with MyHDL, I like it, and I'd like to make  
some synthesizeable code real soon. I don't have any Verilog/VHDL  
experience, maybe my questions are very basic.

All the examples I've seen of MyHDL->Verilog has a set number of  
input/output signals. I'd like to create a program which has all the  
signals inside a list (to be more flexible).

Consider the following example:

def make_many_sregs(clk,din,WIDTH,out,reset,enable,NR_REGS):
     inst = [shiftreg(clk,din[i],WIDTH,out[i],reset,enable) for i in  
range(NR_REGS)]
     return inst

def convert_shiftregister_to_verilog():
     clk,reset,enable = [Signal(bool(0)) for i in range(3)]
     WIDTH=8
     NR_REGS=2
     out = [Signal(intbv(0)[WIDTH:]) for i in range(NR_REGS)]
     din = [Signal(bool(0)) for i in range(NR_REGS)]

     toVerilog.name="shiftregister"
     toVerilog(make_many_sregs,clk,din,WIDTH,out,reset,enable,NR_REGS)

The intention is that NR_REGS gives how many shift-registers I'd like. I  
make the same number of data in and parallel out Signals as  
shift-registers.
This is the generated Verilog code. Where are din/out signals?

module shiftregister (
     clk,
     reset,
     enable
);

input clk;
input reset;
input enable;

wire _inst_2_din;
reg [7:0] _inst_2_pout;
reg [7:0] _inst_2_regi;
wire _inst_1_din;
reg [7:0] _inst_1_pout;
reg [7:0] _inst_1_regi;
wire _inst_0_din;
reg [7:0] _inst_0_pout;
reg [7:0] _inst_0_regi;

If I didn't put the signals in lists, but instead had separate variables  
for each signal, e.g. out1, out2, out3 and din1, din2, din3, the module  
will become different:

def  
make_many_sregs(clk,din1,din2,din3,WIDTH,out1,out2,out3,reset,enable,NR_REGS):
     inst=[]
     inst.append(shiftreg(clk,din1,WIDTH,out1,reset,enable))
     inst.append(shiftreg(clk,din2,WIDTH,out2,reset,enable))
     inst.append(shiftreg(clk,din3,WIDTH,out3,reset,enable))
     return inst

def convert_shiftregister_to_verilog():
     clk,reset,enable = [Signal(bool(0)) for i in range(3)]
     WIDTH=8
     NR_REGS=3
     out1,out2,out3=[Signal(intbv(0)[WIDTH:]) for i in range(NR_REGS)]
     din1,din2,din3 = [Signal(bool(0)) for i in range(NR_REGS)]

     toVerilog.name="shiftregister"
     toVerilog(make_many_sregs,clk,din1,din2,din3,WIDTH,out1,out2,out3,reset,enable,NR_REGS)


Now the Verilog module has more input/output parameters:

module shiftregister (
     clk,
     din1,
     din2,
     din3,
     out1,
     out2,
     out3,
     reset,
     enable
);

input clk;
input din1;
input din2;
input din3;
output [7:0] out1;
reg [7:0] out1;
output [7:0] out2;
reg [7:0] out2;
output [7:0] out3;
reg [7:0] out3;
input reset;
input enable;


I also get complaints that Signals are either not driven or used when  
keeping signals in a list.

Since in both cases, the design that is converted will be of a specified  
size (number of shift-registers) how are they different?

I'm sorry if this an absurd question.


Thanks,
Jens Petter Abrahamsen