[myhdl-list] Re: Newbie question

[Jan D. <ja...@ja...>]

Jamie Guinan wrote:
> Hi!
> 
> I'm just getting started with MyHDL.  In fact, this is my first 
> experience with digital electronics modelling, but since I know Python 
> pretty well (I use it for about 50% of my work), MyHDL looks like a 
> great way to get started.
> 
> My question: if I have a 4-bit output signal, how can I isolate 1 bit 
> to use as an input to another item that takes a 1-bit input signal?

In MyHDL, you will have to explicitly create a 1-bit signal, e.g.

event = Signal(bool(0))
@always_comb
def driveEvent():
     event.next = output[0]

In MyHDL, slice/index operations on a Signal are not signals themselves,
but are simply delegated to the corresponding access on the current
value (as with all other operators.)

In languages like VHDL/Verilog, you can get the behavior that you
expect. Therefore, this is a weak point of MyHDL (and in fact I'm
surprized that this is the first time it was reported :-)). But
I think here we are at the limits of what you can expect from
a "scripting" language. In VHDL/Verilog, a compilation step can
disambuigate between "structural" usage (as a signal) and
"behavioral" usage (as a value.) Without such a step, the
possibilites are much more restricted.

Of course, I thought about the possibility to implement slice/index
operations that return new Signals, but this becomes very
complicated. s and s[i] are then not just separate signals, but
any assignment to either one should have the appropriate effect
in the other one. Not simple.

So I decided to keep it simple and rely on the user for explicit
"conversions" between the views where appropriate. Note that in
a higher-level design style (less signals), such conversions
should be much less required than in a lower-level design style
(with a lot of structure and signals).

Moreover, MyHDL does have a feature that can help in the
structure view: lists of signals. Instead of using
a single wide signal to start with, you can use individual signals
grouped in a list to describe iterative structures.

It is also possible to create generic modules
that convert between a wide signal and a list of signals,
and vice versa.

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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