[myhdl-list] Newbie question

[Jamie G. <gu...@bl...>]

Hi!

I'm just getting started with MyHDL.  In fact, this is my first 
experience with digital electronics modelling, but since I know Python 
pretty well (I use it for about 50% of my work), MyHDL looks like a 
great way to get started.

My question: if I have a 4-bit output signal, how can I isolate 1 bit 
to use as an input to another item that takes a 1-bit input signal?

Here's an example, see the comments near the bottom.

<code>
#!/usr/bin/python

from myhdl import *

def ClkDriver(clk):
    halfPeriod = delay(1)
    @always(halfPeriod)
    def driveClk():
        clk.next = not clk
        # print 'clk: %s' % now()
    return driveClk


def BcdDownCounter(clk, Qout):
    @always(clk.posedge) 
    def downCount():
        if Qout == 0:  
            Qout.next = Qout + 9
        else:
            Qout.next = Qout - 1
        print 'bcd: %s' % Qout.next
    return downCount

def Trigger(input):
    @always(input.posedge)
    def logic():
        print 'trigger'
    return logic


output = Signal(intbv(0)[4:])
input = Signal(bool(0))
clk = Signal(0)

clock_inst = ClkDriver(clk)
counter_inst = BcdDownCounter(clk, output)

if 1:
    # This works, for illustration, but isn't what I'm after:
    trigger_inst = Trigger(clk)

## Here's some of my failed attempts:
if 0:
    # This returns a bool, not a Signal, so it fails with
    #  AttributeError: 'bool' object has no attribute 'posedge'
    trigger_inst = Trigger(output[0])

if 0:
    # Signal initialized only with intial value, does not track output[n]
    trigger_inst = Trigger(Signal(output[0]))

# The simulation.
sim = Simulation(clock_inst,
                 counter_inst,
                 trigger_inst)
sim.run(40)
</code>

Thanks,
-Jamie