[myhdl-list] Adoption / verilog parser/stub gen

[Ken H. <gen...@gm...>]

I've just read the stopwatch example, and it certainly seems like MyHDL
can provide a productivity benefit for HDL development. I'd like to use
it for a project or two I'm working on, however there is one main
barrier to adoption for me.

The projects are typically very modular, and even leaf nodes in the
hierarchy need to call vendor modules (eg block rams, DSP slices). The
current support for black box modules - as I understand it - means I
need to create a stub python module for the verilog one, and then
declare that certain signals are being driven by the block. This seems
sane and reasonable. However, what would *really* drive adoption for me,
would be to be able to point MyHDL at a directory of verilog modules and
have it generate the stubs, including output drivers based on the output
signals in the verilog code.

Ultimately full round-trip in/out of MyHDL/verilog would be ideal, but
stub generation would probably tip the balance for me. I'm currently 
working on an antlr based tool, which will do this, but thought I'd 
float the idea to see if it already exists.

Ken.