[myhdl-list] Re: state machines etiquette
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From: Jan D. <ja...@ja...> - 2006-03-06 23:02:54
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George Pantazopoulos wrote: > Hi all, > > In general for state machines is it a must to specify all the outputs > at every state? Sometimes I just want an output to stay the same until I > explicitly tell it to change, which seems necessary sometimes, and also > results in more readable code. However, is this advisable? There is no technical reason to do anything else than keeping the code as readable as possible. The "state machine" paradigm is somewhat outdated with modern HDLs and synthesis. Keeping a signal to its value is implemented as efficiently as giving it a specific value. A related issue is when you want to specify the same value for an output most of the time, and another one in a specific state (and perhaps under special conditions) only. Use a default value in that case: sig.next = <default value> if state == ... ... elif state == ... ... if <special case>: sig.next = <special value> elif ... ... else: ... Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Losbergenlaan 16, B-3010 Leuven, Belgium From Python to silicon: http://myhdl.jandecaluwe.com |