[myhdl-list] Re: signed multiplication

[Jan D. <ja...@ja...>]

Haitao Zhang wrote:
> 
> Does myHDL now support signed vector and how?

It has always been possible to use negative intbv's - but until
0.5 it was not possible to convert them to Verilog. I assume
that's what you mean. Signed support for Verilog conversion
in 0.5 is described here:

http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5#support_for_signed_arithmetic

> Without signed number support specifying a signed multiplication (or 
> other arithmetics) is quite awkward.  It is also non-optimal for synthesis.

I'll give an example to clarify. Consider:


     from myhdl import *

     def test(c, a, b):

         @always_comb
         def mult():
             c.next = a * b

         return mult


to describe a multiplication. As always, you can convert a
design instance to Verilog. For negative intbv's you have to
constrain them using an integer range, not a bit slice. Note
that this is higher level view than working with bit vectors,
entirely appropriate for arithmetic and much less error-prone.
For example:

     a = Signal(intbv(0, min=-9, max=45))
     b = Signal(intbv(0, min=-24, max=45))
     c = Signal(intbv(0, min=-1000, max=1000))

     toVerilog(test, c, a, b)

The Verilog output is:

     module test (
         c,
         a,
         b
     );

     output signed [10:0] c;
     wire signed [10:0] c;
     input signed [6:0] a;
     input signed [6:0] b;

     assign c = (a * b);

     endmodule


Note how signed regs are used. Now, consider a
different conversion:

     a = Signal(intbv(0, min=0, max=45))
     b = Signal(intbv(0, min=-24, max=45))
     c = Signal(intbv(0, min=-1000, max=1000))

     toVerilog(test, c, a, b)

Then the output is:

     module test (
         c,
         a,
         b
     );

     output signed [10:0] c;
     wire signed [10:0] c;
     input [5:0] a;
     input signed [6:0] b;

     assign c = ($signed({1'b0, a}) * b);

     endmodule

Now the convertor uses an unsigned reg for a, but adds a
sign bit and a cast to it in the multiplication. It's for this reason
that I claim that working with negative numbers is much easier
in MyHDL than in Verilog: the error-prone issues with regard to
signed representation are taken care of by the convertor.

Ain't it great :-)?

Jan


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
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