[myhdl-list] Re: Cosimulation with the simple FSM example.

[Jan D. <ja...@ja...>]

Brendan Rankin wrote:
> Brendan Rankin <brendan.rankin <at> gmail.com> writes:
> 
> 
>>Please let me know if you spot anything that you feel is in err.
>>
>>Thanks, in advance, and Best Regards,
>>
>>- Brendan
> 
> 
> 
> Nevermind.  Found the "x" issue.  For every clock, prior to the reset event, the
> state was being assigned x's.

Yes, this is a classical initialization issue: a difference between
the initial value of a high-level type (some enum item) and its
low level equivalent ('x').

At some point, I used initial values in reg declaration in the
Verilog output, as supported by recent Verilogs. This
would solve this issue (but of course it would mask potential
reset problems, just like in the high-level code). However,
it turns out that many currently used tools don't support
them yet. So I took this out for now.

Thinking about it, for implementation purposes it may be
better to collapse the final state with the default
case (the 'else' in MyHDL), or remove the default
alltogether.

Regards,

Jan

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