Re: [myhdl-list] Re: Cosimulation with the simple FSM example.
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jandecaluwe
From: George P. <ge...@ga...> - 2006-01-04 20:18:54
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> > In one of my modules where I tried using the enum, I > > noticed that I got incorrect behavior (incorrect initial states, I > > believe) if I didn't specify the encoding style. It worked correctly > > when I specified 'encoding=3Done_cold'. I haven't tried other encodi= ng > > styles. > >> This was in the synthesized hardware (Xilinx ISE w/XST). I didn't >> co-simulate this module. Is this dependence on encoding type something >> to >> be expected when doing synthesis? > > Certainly not. It should always work. Out of the 3 possible encodings > the default (binary) is the "least risky": as the initial > state will be all zero's (often the default in fpga's), things may stil= l > work when your reset sequence doesn't work as it should. Moreover, > once in the Verilog domain, binary encoding is basically identical > to the simplest use of plain integers. So the problems you report > are the opposite of what I would expect, and I haven't a clue > on what went wrong. > > Cosimulation may help to clarify things in the future :-) > > Jan Yeah, I think I will try that. Also, I want to try making it easier to do co-simulation/unit testing. I'm doing my project for fun, and often I fee= l it hampers the fun and creativity if I have to write up (and debug!) a unit test every time I add or change a component. I feel my last attempt at incorporating unit testing in my design flow wa= s somewhat successful, however I really didn't like having to spend time debugging the unit tests themselves! This may be easier now that I'm more experienced with Python, myHDL, co-simulation, and hardware design (that'= s a lot of things to learn at once, on top of extreme programming!). Unit testing and co-simulating *everything* still doesn't feel natural to me, and I'm not sure if it ever will. Speaking of promotional breaks, have you seen the new colorful photos I took of my project? :-) http://myhdl.jandecaluwe.com/doku.php/projects:phoenixsid_65x81 George |