[myhdl-list] Re: Cosimulation with the simple FSM example.

[Brendan R. <bre...@gm...>]

Jan Decaluwe <jan <at> jandecaluwe.com> writes:

> Please consider posting the code you're using. It always saves time
> when troubleshooting.
> 
> Best regards,
> 
> Jan

Jan,

I'll probably enhance the enum type in the near future to better handle this.
It's not a big deal anyway....  

Here's the code you requested -- Python code that simulates the FSM and
generates the Verilog, first:

====Begin====
from myhdl import *

t_State = enum('SEARCH', 'CONFIRM', 'SYNC', encoding='one_hot')
ACTIVE_LOW = 0
FRAME_SIZE = 8

def FramerCtrl(SOF, state, syncFlag, clk, reset_n):
   """Framing control FSM.

   SOF => start-of-frame output bit
   state => FramerState output
   syncFlag => sync pattern found indication bit
   clk => clock input
   reset_n => active low reset
   """

   index = Signal(intbv(0)[8:]) #position in frame...
   
   @always(clk.posedge, reset_n.negedge)
   def FSM():
      if reset_n == ACTIVE_LOW:
         SOF.next = 0
         index.next = 0
         state.next = t_State.SEARCH
         
      else:
         index.next = (index + 1) % FRAME_SIZE
         SOF.next = 0

         
         if state == t_State.SEARCH:
            index.next = 1
            if syncFlag:
               state.next = t_State.CONFIRM

               
         elif state == t_State.CONFIRM:
            if index == 0:
               if syncFlag:
                  state.next = t_State.SYNC
               else:
                  state.next = t_State.SEARCH

                     
         elif state == t_State.SYNC:
            if index == 0:
               if not syncFlag:
                  state.next = t_State.SEARCH
            SOF.next = (index == FRAME_SIZE-1)

               
         else:
            print "State = %" % state
            raise ValueError("Undefined state")

   return FSM

def testbench():
   SOF = Signal(bool(0))
   syncFlag = Signal(bool(0))
   clk = Signal(bool(0))
   reset_n = Signal(bool(1))
   state = Signal(t_State.SEARCH)

   framerctrl = FramerCtrl(SOF, state, syncFlag, clk, reset_n)

   @always(delay(10))
   def clkgen():
      clk.next = not clk

   @instance
   def stimulus():
      reset_n.next = 1
      yield delay(50)
      reset_n.next = 0
      yield delay(50)
      reset_n.next = 1
      for i in range(20):
         yield clk.posedge
      for n in (12, 8, 8, 4):
         syncFlag.next = 1
         yield clk.posedge
         syncFlag.next = 0
         for i in range(n-1):
            yield clk.posedge
      raise StopSimulation

   return framerctrl, clkgen, stimulus

def GenWaveform():
   tb_fsm = traceSignals(testbench)
   sim = Simulation(tb_fsm)
   sim.run()

def GenVerilog():
   SOF = Signal(bool(0))
   syncFlag = Signal(bool(0))
   clk = Signal(bool(0))
   reset_n = Signal(bool(1))
   state = Signal(t_State.SEARCH)
   frmrctrl_inst = toVerilog(FramerCtrl, SOF, state, 
                             syncFlag, clk, reset_n)

GenWaveform()
GenVerilog()
=====End=====

Here, also, are the simple changes I made to cosimulate:

=====Begin=====
cmd = "iverilog -o FramerCtrl.o " + \
      "FramerCtrl.v " + \
      "tb_FramerCtrl.v "

def FramerCtrl(SOF, state, syncFlag, clk, reset_n):
   os.system(cmd)
   return Cosimulation("vvp -m <some_long_path>/myhdl.vpi FramerCtrl.o",
                        SOF=SOF, state=state, syncFlag=syncFlag,
                        clk=clk, reset_n=reset_n)
=====End=====

Please let me know if you spot anything that you feel is in err.

Thanks, in advance, and Best Regards,

- Brendan