Re: [myhdl-list] state enum trouble

[George P. <ge...@ga...>]

>>
>>   When I used the state enum in the code below, the Verilog output 
>> caused an XST Error (pasted below too). It seems that the case 
>> statement refers to the nonexistent name (in the verilog code) 
>> 'state', when it should have been the 'fully qualified' name 
>> '_synthInst_SID_INST_envGen0_state'. When I fixed the Verilog code by 
>> hand, it compiled, synthesized and worked correctly. I saw this in 
>> both myhdl 0.5a1 and 0.5b1.
>>
>> Hope this helps squish a bug before the big 0.5 release :)
>
>
> Of course, a customer with a problem always gets priority :-)
>
> I have solved the bug in the code. Thanks for the report.
>
Thanks, you're the best :-) Could I get the changed file(s)?

Happy Christmahanuquanzica :)

George