[myhdl-list] state enum trouble

[George P. <ge...@ga...>]

Hi Jan,

   When I used the state enum in the code below, the Verilog output 
caused an XST Error (pasted below too). It seems that the case statement 
refers to the nonexistent name (in the verilog code) 'state', when it 
should have been the 'fully qualified' name 
'_synthInst_SID_INST_envGen0_state'. When I fixed the Verilog code by 
hand, it compiled, synthesized and worked correctly. I saw this in both 
myhdl 0.5a1 and 0.5b1.

Hope this helps squish a bug before the big 0.5 release :)

Thanks,
George


// Excerpt of myHDL code //

def EnvelopeGen(clk, gate, attack_rate, decay_rate, sustain_level, 
release_rate, reset_n, env_out, accum_width=24):
   
    accum = Signal(intbv(0)[accum_width:])
   
    t_State = enum('Idle', 'Attack', 'Decay', 'Sustain', 'Release')
    state = Signal(t_State.Idle)
   
    @always(clk.posedge)
    def EnvGenProcess():
       
        env_out.next = accum[accum_width:accum_width-len(env_out)]
       
        if state == t_State.Idle:
            accum.next = 0
            if gate:
                state.next = t_State.Attack

        elif state == t_State.Attack:
            accum.next = (accum + 8) % 2**accum_width
            if gate == False:
                state.next = t_State.Idle
               
        else:
            state.next = t_State.Idle

   
    return instances()


===== Excerpt of resulting Verilog code ==========

// ...

reg [2:0] _synthInst_SID_INST_envGen0_state;

// ...
// ... Much more stuff in between
// ...

always @(posedge clk) begin: _top_synthInst_SID_INST_envGen0_EnvGenProcess
    _synthInst_SID_INST_env0_out <= 
_synthInst_SID_INST_envGen0_accum[24-1:(24 - 12)];
    // synthesis parallel_case full_case
    casez (state)
        3'b000: begin
            _synthInst_SID_INST_envGen0_accum <= 0;
            if (_synthInst_SID_INST_wave0_gate) begin
                _synthInst_SID_INST_envGen0_state <= 3'b001;
            end
        end
        3'b001: begin
            _synthInst_SID_INST_envGen0_accum <= 
((_synthInst_SID_INST_envGen0_accum + 8) % (2 ** 24));
            if ((_synthInst_SID_INST_wave0_gate == 0)) begin
                _synthInst_SID_INST_envGen0_state <= 3'b000;
            end
        end
        default: begin
            _synthInst_SID_INST_envGen0_state <= 3'b000;
        end
    endcase
end


=== Xilinx XST Error =======

Started process "Synthesize".

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "../../phoenixSID.v"
ERROR:HDLCompilers:28 - "../../phoenixSID.v" line 114 'state' has not 
been declared
Module <phoenixSID> compiled
Analysis of file <"phoenixSID.prj"> failed.
-->

Total memory usage is 88628 kilobytes

Number of errors   :    1 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.