[myhdl-list] Re: Issue with toVerilog.name and traceSignals.name

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
>>>1) only be used for the output filename ("my_name.v")
>>>2) also for the name of the actual toplevel Verilog module
>>>
>>>Prior to 0.5b1, option 2) was implemented. The problem is that
>>>you may set it to a name which is already used elsewhere in the code,
>>>creating a problem in the output. This is not checked by MyHDL.
>>>So for 0.5b1, I though I needed to fix that and changed
>>>it to option 1).
> 
> 
> I prefer option 2, for consistency.

Ok, option 2) it will be for 0.5 final.

 > Is there a fundamental reason that
> myHDL can't check for a name clash? :)

No, but thinking about it the problem is larger. It would
be fairly easy to use Verilog keywords in MyHDL code, and
create a problem in converted output. Currently, there
are no checks.

However, the symptoms would be clear (compilation error) and
the workaround trivial. So I will defer a solution (if
required) to later.

Jan

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