Re: [myhdl-list] Issue with toVerilog.name and traceSignals.name

[George P. <ge...@ga...>]

>> 1) only be used for the output filename ("my_name.v")
>> 2) also for the name of the actual toplevel Verilog module
>>
>> Prior to 0.5b1, option 2) was implemented. The problem is that
>> you may set it to a name which is already used elsewhere in the code,
>> creating a problem in the output. This is not checked by MyHDL.
>> So for 0.5b1, I though I needed to fix that and changed
>> it to option 1).

I prefer option 2, for consistency. Is there a fundamental reason that
myHDL can't check for a name clash? :)

--=20
George Pantazopoulos
http://www.gammaburst.net