Re: [myhdl-list] Issue with toVerilog.name and traceSignals.name

[Tom D. <td...@di...>]

Jan Decaluwe wrote:

>
> 1) only be used for the output filename ("my_name.v")
> 2) also for the name of the actual toplevel Verilog module
>
> Prior to 0.5b1, option 2) was implemented. The problem is that
> you may set it to a name which is already used elsewhere in the code,
> creating a problem in the output. This is not checked by MyHDL.
> So for 0.5b1, I though I needed to fix that and changed
> it to option 1).
>
> Now I'm confused and I think it's really 2) that designers
> want, despite the potential name clash.

I like option 2 better, but either way is OK. I think normally you 
expect the file name and module name to be the same.

Tom