[myhdl-list] Issue with toVerilog.name and traceSignals.name

[Jan D. <ja...@ja...>]

Hi:

In beta release 0.5b1, I may have introduced a problem while trying
to "fix" the behavior of toVerilog.name (and traceSignals.name).

With toVerilog.name, you can set a name other than the default
for the toplevel name. For example:

toVerilog.name = "my_name"

The question is: should that name be used

1) only be used for the output filename ("my_name.v")
2) also for the name of the actual toplevel Verilog module

Prior to 0.5b1, option 2) was implemented. The problem is that
you may set it to a name which is already used elsewhere in the code,
creating a problem in the output. This is not checked by MyHDL.
So for 0.5b1, I though I needed to fix that and changed
it to option 1).

Now I'm confused and I think it's really 2) that designers
want, despite the potential name clash.

Same issue for traceSignals.name, and the output VCD file.

Feedback welcome,

Jan

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