[myhdl-list] any news with regards to tristate I/O?

[George P. <ge...@ga...>]

Hi all,

   I need to interface my FPGA with a device that has a tri-state data
bus. (a FT245BM USB<->FIFO adapter). Do I still need to make a wrapper
in Verilog, or is there a better approach now? Has anyone any
examples/tips to share?

Thanks,
George