[myhdl-list] Re: co-simulation: vpi file

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> Hi Jan, in the util.py file pasted below, what should be assigned to
> verilogCompile if I want to use Icarus and not cver?
> 
> By the way, by commenting out the last two lines of util.py,
> test_always_comb.py and test_fsm.py both passed all tests. However, I
> got an error regarding verilogCompile when I tried to run test_all.py.
> So I need the correct value for it, commenting it out wont do.
> 
> All the test files I mentioned are in myhdl/test/toVerilog.

George:

I reviewed the toVerilog tests with Icarus. I have 2
groups of failures:

- test_bugreports fails because of the missing verilogCompile
- test_inc has a failing test because of a bug in the test suite

I have solved these issues in my development code.

- test_dec has failing tests because of Icarus bugs with signed
- test_signed has failing tests because of Icarus bugs with signed

There's no solution for these ones. Please note that Icarus is
unreliable for signed arithmetic.

I will add notes in the README.txt file in the test/toVerilog
directory to explain the issues.

If you see the same, you can ignore the failures for now and it
basically means that you got it to work on Windows. That is
good news - thanks for the efforts.

For completeness: the verilogCompile only does a compile step
of Verilog code, no cosimulation. The Icarus version is:

def verilogCompileIcarus(name):
     objfile = "%s.o" % name
     if path.exists(objfile):
         os.remove(objfile)
     analyze_cmd = "iverilog -o %s %s.v tb_%s.v" % (objfile, name, name)
     os.system(analyze_cmd)


Regards,

Jan

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