Re: [myhdl-list] Re: co-simulation: vpi file

[George P. <ge...@ga...>]

Hi Jan, in the util.py file pasted below, what should be assigned to
verilogCompile if I want to use Icarus and not cver?

 By the way, by commenting out the last two lines of util.py,
test_always_comb.py and test_fsm.py both passed all tests. However, I
got an error regarding verilogCompile when I tried to run test_all.py.
So I need the correct value for it, commenting it out wont do.

All the test files I mentioned are in myhdl/test/toVerilog.

Thanks,
George




import os
path = os.path

from myhdl import *

# Icarus
def setupCosimulationIcarus(**kwargs):
    name = kwargs['name']
    objfile = "%s.o" % name
    if path.exists(objfile):
        os.remove(objfile)
    analyze_cmd = "iverilog -o %s %s.v tb_%s.v" % (objfile, name, name)
    os.system(analyze_cmd)
    simulate_cmd = "vvp -m ../../../cosimulation/icarus/myhdl.vpi %s" %
objfile
    return Cosimulation(simulate_cmd, **kwargs)

# cver
def setupCosimulationCver(**kwargs):
    name = kwargs['name']
    cmd = "cver -q
+loadvpi=../../../cosimulation/cver/myhdl_vpi:vpi_compat_bootstrap " + \
          "%s.v tb_%s.v " % (name, name)
    return Cosimulation(cmd, **kwargs)

def verilogCompileCver(name):
    cmd = "cver -c %s.v" % name
    os.system(cmd)


setupCosimulation = setupCosimulationIcarus
setupCosimulation = setupCosimulationCver

verilogCompile = verilogCompileCver

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