[myhdl-list] Re: co-simulation: vpi file

[Jan D. <ja...@ja...>]

Günter Dannoritzer wrote:
> George Pantazopoulos wrote:
>  >
> 
>>It seems to ok for me (I compiled icarus 0.82 under cygwin). However, unit
>>tests that pass in the myHDL domain are failing when I run them with
>>co-simulation. Have you had that happen to you before?

Like always, it would help to give details on how it fails on a small
example.

> 
> Only if my myhdl logic would not generate the verilog that I expected it
> to be.

A bug in the Verilog conversion is one possibility.

Other possibilities that should be checked before:

- initialization. What happens at time 0 may be different for Verilog
and MyHDL, e.g. because of X-handling. Make sure all signals should have
a defined value before you start comparing them. Don't compare at
time 0, but after certain events (e.g. clock) or delay have occurred.

- does co-simulation work at all ??? If it does work, the error messages
you get should come from unittest assertion statements, not from
the Cosimulation module.

> 
> Though I did not use co-simulation under cygwin.
> 
> Did you try it with a simple example which allows you to follow it by
> hand to verify the output?

Note that the toVerilog tests (myhdl/test/toVerilog) have plenty of
unit test modules that use co-simulation. All those tests have been
run with cver and icarus. (Exception: test_signed fails with Icarus
because it has bugs with signed arithmetic.)

So for a small example that should work, you may want to look there.

Jan

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