Re: [myhdl-list] Style based on decorators
Brought to you by:
jandecaluwe
From: bedros <be...@ya...> - 2005-12-02 18:50:32
|
I disagree with Matt, and agree with Jan. This is still an experimental release (sub 1.0) meaning major changes could happen. I think decorators are brilliant idea; and make it look like a real HDL rather than a hacked sequential language as in the old style. I would prefer to stay compatible with old style as long it does not conflict with the new style; but compatibality is not important. I believe that the most important advantage with MyHDL over other HDL's is the ability to express my designs in the language in the least effort; and the ability to read and understand the code without trying to crack the cryptic ways of making it a parallel language. Decorators simplify things and make coding in MyHDL more elegant. to me, MyHDL is to RTL design, is like what FPGA is to ASIC. It's a way of getting something out quickly. It's a fast way from concept to a cycle acurate model of the concept; and run the design in simulation, to verify the architecture; if things work well, I could try toVerilog conversion; or replace parts of the design with their equivalent verilog or VHDL by hand; In my work, we do everything in VHDL; I wonder if it's possible to co-simulate VHDL and MyHDL via VHPI interface; I don't need it right now, but probably in a year; I'll try to figure it out. keep the good work Jan. -Bedros --- Matt Ettus <ma...@et...> wrote: > Jan Decaluwe wrote: > > Hi: > > > > I have decided to proceed with the introduction of > decorators > > to create local generators in 0.5. > > > > In addition, I would like to make this the default > coding style. > > In particular, I would change all documentation > and examples to > > use decorators, including in tutorials. Note that > 3 decorators > > are introduced: @always, @always_comb, and > @instance. > > > > Also, the possibility to use a parametrizable > generator directly > > would be de-emphasized (but possible, of course). > The equivalent > > in VHDL/Verilog would be a process/always block > with a port > > interface, something which doesn't exist. > Therefore, this > > can be confusing to new users. Instead, one would > use a function > > that returns a single generator (as many of you do > already). > > This makes the overall style more consistent: > structure is > > always specified using a plain function, behavior > using > > a local generator (created with a decorator). > > > > Note that all of this has no impact on backwards > compatibility. > > > > As always, let me know if you disagree. > > I don't see the advantage of pushing everyone > towards the decorators. > Am I correct in my understanding that complex cases > may still need the > old syntax? > > Also, I love Python and understand the desire to be > Pythonic, but making > things as different as possible from preexisting > HDLs doesn't seem to > buy anything but a steep learning curve. > > Matt > > > ------------------------------------------------------- > This SF.net email is sponsored by: Splunk Inc. Do > you grep through log files > for problems? Stop! Download the new AJAX search > engine that makes > searching your log files as easy as surfing the > web. DOWNLOAD SPLUNK! > http://ads.osdn.com/?ad_id=7637&alloc_id=16865&op=click > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list > |