Re: [myhdl-list] Re: Problems inferring RAM when it is buried in system

[George P. <ge...@ga...>]

> George Pantazopoulos wrote:
>> Dear Jan and  Tom,
>>
>> I have created a simplified, representative mock-up of my system. When
>> this code is processed with myHDL (0.5dev1) and Xilinx ISE WebPACK
>> 7.1.04i, no RAM's are inferred. However, using the same RAM function i=
n
>> a trivial standalone example results in inferred RAM.
>>
> George:
>
> I have been able to reproduce your issue.
>
> By now I'm pretty sure that the problem is not related to embedded
> code, but to the fact that the design is not clean.
>

Jan, you were right. I tweaked my ram_inference_test_embedded.py example
to eliminate two signals that generated "assigned but never used" XST
warnings, and magically, a block ram got synthesized! :) Now I have to do
this with my real system, which will be more difficult.

However, at this point I think I should rewrite it from scratch with unit
testing and co-simulation in mind. Besides the online manual, do you know
of any other complete examples or other resources to help get me started?

Thanks,
George