Re: [myhdl-list] Re: Problems inferring RAM when it is buried in system

[George P. <ge...@ga...>]

Hi Tom,

> It can't be stressed enough that the proper flow for logic design with
> MyHDL is the following:
>
> 1. MyHDL logic unittest, used here and in steps 2 and 4.

  It seems that some unit tests I would want to do require a human in the
loop. Examples would be verifying that sounds are being produced, or
certain messages displayed on an LCD screen. How do these fit into this
flow, if the flow is to be automated?

  Rather than unit tests, I've been doing test-benches and viewing the
resulting waveforms with gtkwave. I'm running into the probem quite
often that my system looks great in simulation, but does not work
correctly (or at all sometimes) after being synthesized.

  I'd like to add unit tests to my flow, but I could really use some
guidance and example code for this. What should I unit test? Should a
unit test always be completely automated, etc?

> 2. Apply unittest to toVerilog logic via cosimulation.

  Could you tell me about co-simulation? I've had a tough time browsing
the web looking for non-expert information about it. How would I go
about doing this with myHDL and other free/low-cost tools?

> 3. toVerilog logic synthesis with your favorite synthesis tool.
> 4. post synthesis unittest.
>
> If logic changes are required after step 4, all steps should be
> repeated. Note, these can all be automated from the MyHDL unittest.

Thanks,

George Pantazopoulos
http://www.gammaburst.net